1. Field of the Invention
The present invention relates to a printed circuit board on which a semiconductor such as an IC package is mounted.
2. Description of the Related Art
In recent years, along with realization of high speed operation and high integration in an electronic device, a power ground noise of a semiconductor integrated circuit (IC chip) mounted on a printed wiring board in the electronic device tends to increase. The power ground noise is generated by a sudden variation of the current consumed by the IC chip when the current flows in a power supply wiring of the printed wiring board or a semiconductor package. FIGS. 12A and 12B illustrate a general frequency characteristic of the power ground noise. In FIG. 12A, the abscissa indicates frequency and the ordinate indicates the amount of generated power ground noise. The amount of generated power ground noise in the IC chip increases at plural frequencies which depend on the operating frequency of the IC chip. When the amount of generated power ground noise exceeds a threshold value, a signal transmission timing of the IC chip under operation varies, so a malfunction of the electronic device occurs.
In order to reduce the power ground noise, a method of providing a bypass capacitor between a power supply wiring and a ground (GND) wiring near the IC chip has been generally known. The characteristic of the bypass capacitor also depends on frequency, so the bypass capacitor is not always effective for all frequencies. FIG. 12B illustrates a general characteristic of the bypass capacitor. In FIG. 12B, the abscissa indicates frequency and the ordinate indicates impedance of the bypass capacitor. As is apparent from FIG. 12B, the impedance of the bypass capacitor becomes significantly low at one frequency (resonance frequency). That is, although the power ground noise can be reduced in one frequency (resonance frequency) band, the power ground noise cannot be sufficiently reduced in other frequency bands than such frequency band. That is, the frequency is typically determined based on capacitance of the bypass capacitor and inductance of a supply path up to the bypass capacitor. The resonance frequency of the bypass capacitor can be obtained by the following expression (1).
                    F        =                  1                      2            ⁢            π            ⁢                          LC                                                          (        1        )            That is, with regard to the resonance frequency F, capacitance C of the bypass capacitor and inductance L between the IC chip and the bypass capacitor are changed to shift the resonance frequency, so it is possible to change the frequency band at which an effect of the bypass capacitor can be expected. In other words, when the frequency at which the power ground noise generated from the IC chip is large is set as the resonance frequency of the bypass capacitor, effective power ground noise reduction can be realized.
It has been known that the bypass capacitor located at distance as close as possible from the power supply terminal and the GND terminal of the IC chip effectively acts on the power ground noise. That is, when the inductance of a wiring connecting between the IC chip and the bypass capacitor is reduced, current can be supplied to the IC chip more steeply, so it is possible to reduce the power ground noise. When the propagation path (propagation loop) of a signal which carries the power ground noise is shortened, radiation noise resulting from the power ground noise can be also reduced.
U.S. Pat. No. 6,384,476 discusses a configuration of a bypass capacitor in a printed circuit board on which a ball grid array (BGA) type semiconductor package is mounted. According to U.S. Pat. No. 6,384,476, the power supply terminal and the GND terminal of the semiconductor package are located adjacent to each other. The power supply wiring and the GND wiring are led from the power supply terminal and the GND terminal to the back surface of the printed wiring board through a through hole and connected with each other through the bypass capacitor. Therefore, the physical distance between the IC chip and the bypass capacitor is shortened to reduce inductance of the power supply wiring and inductance of the GND wiring, thereby reducing the power ground noise.
Japanese Patent Application Laid-Open No. H09-139573 discusses a method of reducing the power ground noise using an LC filter which includes a bypass capacitor and an inductor which are provided in an IC package. The bypass capacitor is located in the IC package, so the distance between the IC chip and the bypass capacitor is further shortened.
Japanese Patent Application Laid-Open No. 2003-318352 discusses that voltage conversion is performed by a step-down circuit of an IC package to obtain a core power source and the core power is supplied to an IC chip of the IC package. In this case, a core voltage terminal is provided for the IC package, and the core power source is stabilized by a bypass capacitor on a printed wiring board.
As discussed in U.S. Pat. No. 6,384,476 and Japanese Patent Application Laid-Open Nos. H09-139573 and 2003-318352, when the bypass capacitor is used, the power ground noise corresponding to the operating frequency of the IC chip can be reduced. However, the power ground noise generated in an inner portion of the IC chip causes not only a malfunction due to a variation in timing of the IC chip under operation and the like but also a malfunction of another IC chip and the generation of an EMI noise in the case where the power ground noise propagates to the power supply side. In particular, it is difficult to predict the EMI noise in the design phase, so the reduction thereof is a serious problem.
Here, a problem with respect to the propagation of the power ground noise to another IC chip in a circuit using a normal bypass capacitor will be described with reference to a result obtained by simulation.
FIG. 13 illustrates a circuit model in which bypass capacitors are provided. Calculation was performed through a simulation using the circuit model. A source power supply 201 and an IC chip 211 are assumed. The purpose of this simulation is to evaluate the characteristic of the power supply path between the source power supply and the IC chip, so the source power supply and the IC chip are assumed as an input or output of the power supply path and are thus not modeled.
The power supply path between the source power supply 201 and the IC chip 211 is modeled with power supply paths 202a, 202b, and 202c. It is assumed that the power supply path 202a is a line whose width is 50 mm and length is 50 mm, L=4.9e-09 H/cm, C=9.5454e-09 F/cm, R(DC)=0.011 Ω/cm, Rs=4.01609262841384e-06 (Ω·ns) 0.5/cm, and Gd=1.718589e-10 mS/cm. It is assumed that the power supply path 202b is a line whose width is 8 mm and length is 3 mm, L=2.15e-08 H/cm, C=2.1492e-09 F/cm, R(DC)=0.066 Ω/cm, Rs=2.36854596746612e-05 (Ω·ns) 0.5/cm, and Gd=3.86858e-11 mS/cm. Ts is assumed that the power supply path 202c is a line whose width is 8 mm and length is 20 mm, L=2.15e-08 H/cm, C=2.1492e-09 F/cm, R(DC)=0.066 Ω/cm, Rs=2.36854596746612e-05 (Ω·ns) 0.5/cm, and Gd=3.86858e-11 mS/cm. Note that Rs represents a resistance component obtained due to a skin effect, and Gd represents a parameter for dielectric loss.
The GND wiring path between the IC chip 211 and the source power supply 201 is modeled with GND paths 203a, 203b, and 203c. Each of the GND paths 203a, 203b, and 203c has a characteristic approximated by 0. A low-frequency bypass capacitor 221 is provided between the connection point located between the power supply paths 202a and 202b and the connection point located between the GND paths 203a and 203b. The capacitance of the bypass capacitor 221 is set to 0.1 pF (parasitic inductance 0.5 nH×2). A high-frequency bypass capacitor 222 is provided between the connection point located between the power supply paths 202b and 202c and the connection point located between the GND paths 203b and 203c. The capacitance of the bypass capacitor 222 is set to 1000 pF (parasitic inductance 0.5 nH×2) obtained by the following expression (2).
FIG. 14A illustrates a Z11 (impedance) characteristic in the case where the circuit model of FIG. 13 is observed from the IC chip 211. As the value of the Z11 characteristic is decreased, the power supply for the IC chip is stabilized at the frequency thereof, so the IC chip has a high resistance to the power ground noise. In FIG. 14A, the resonance point of a low impedance in the vicinity of 10 MHz may be caused by the bypass capacitor 221, and the resonance point of a low impedance in the vicinity of 100 MHz may be caused by the bypass capacitor 222. The resonance point at a higher frequency may be caused by a characteristic of the entire power supply including the power supply paths 202a, 202b, and 202c. That is, the power ground noise in the vicinity of 10 MHz can be reduced by the bypass capacitor 221 and the power ground noise in the vicinity of 100 MHz can be reduced by the bypass capacitor 222.
FIG. 14B illustrates an S21 (transmission) characteristic from the IC chip 211 to the power supply 201 in the circuit model of FIG. 13. The S21 characteristic will be described with reference to FIGS. 15A and 15B. In FIG. 15A, a four-terminal circuit 300 to be measured includes an input side power supply terminal 301a, an input side GND terminal 302a, an output side GND terminal 301b, and an output side power supply terminal 302b. An IC chip 320 is distinct from the IC chip 211, to which power is supplied from the source power supply 201. The S21 characteristic of the four-terminal circuit network when observed from the input side power supply terminal 301a and the input side GND terminal 302a is the signal propagation characteristic at each frequency, to the output side power supply terminal 301b and the output side GND terminal 302b. Therefore, the S21 characteristic exhibits that, as the value thereof is reduced, the power ground noise generated in the IC chip is hard to propagate to the power supply side. That is, it is possible to reduce the influence of the power ground noise on another IC chip (IC 320 in FIG. 15B), to which a voltage of the same potential is supplied from the source power supply 201, which also supplies the voltage to the IC chip 211.
The S21 characteristic from the IC chip 211 to the power supply 201 in the circuit model of FIG. 13 is a transmission characteristic from the input side power supply terminal 301a to the output side power supply terminal 301b through the four-terminal circuit 300 in FIG. 15A.
In FIG. 14B, the point at which the S21 characteristic is high in the vicinity of 10 MHz may be caused by the influence of the bypass capacitor 221, and the point at which the S21 characteristic is high in the vicinity of 100 MHz may be caused by the influence of the bypass capacitor 222. The resonance point at a higher frequency may be caused by the characteristic of the entire power supply including the power supply paths 202a, 202b, and 202c. That is, the power ground noise at frequencies close to 10 MHz and 100 MHz are liable to be propagated to the outside through the power supply of the IC chip by the bypass capacitors 221 and 222.
FIG. 14C is an enlarged portion, in the frequency range (100 MHz to 200 MHz) which is close to the resonance point of the bypass capacitor 222, of a graph illustrating that the Z11 characteristic of FIG. 14A is superimposed on the S21 characteristic of FIG. 14B in the case of the circuit structure of FIG. 13. As is apparent from the Z11 characteristic of FIG. 14C, the resonance point at which the bypass capacitor 222 acts most effectively is within a frequency band close to 138 MHz. In contrast, the frequency band in which the S21 characteristic deteriorates is close to 147 MHz. Therefore, when the resonance frequency of the bypass capacitor 222 is adjusted to a frequency at which the power ground noise is maximum (138 MHz), the impedance of the IC chip at the resonance frequency reduces to reduce the power ground noise. However, the resonance frequency is significantly close to the frequency band in which the S21 characteristic deteriorates, so the power ground noise propagated to the outside becomes larger.
As a result of concentrated studies, the inventor(s) of the present invention found that the frequency band of the bypass capacitor in which the S21 characteristic deteriorates is always present close to the resonance point in the Z11 characteristic. This may be because, in FIG. 13, when the power ground noise at the frequency close to the resonance point of the bypass capacitor 222 will actively flow toward the bypass capacitor 22 at the connection point located between the power supply paths 202b and 202c for supply, a part of the power ground noise is leaked from the connection located between the power supply paths 202b and 202c for supply to the power supply side in a case where the flow toward the bypass capacitor 222 is strong.
Therefore, in the case of the circuit structure using the bypass capacitor as discussed in U.S. Pat. No. 6,384,476 and Japanese Patent Application Laid-Open Nos. H09-139573 and 2003-318352, the power ground noise propagated from the IC chip to the power supply side becomes larger in the frequency band close to the resonance frequency of the bypass capacitor.
(Second Problem)
In addition, in the case of the circuit structure using the bypass capacitor as discussed in U.S. Pat. No. 6,384,476 and Japanese Patent Application Laid-Open Nos. H09-139573 and 2003-318352, it was difficult to accurately determine the resonance frequency of the bypass capacitor. That is, in order to determine the resonance frequency, it was necessary to model all complicated power supply paths to perform a simulation.
In order to exhibit the fact that it is difficult to accurately determine the resonance frequency of the bypass capacitor, calculation was performed by a simulation using a circuit model illustrated in FIG. 16. The circuit model illustrated in FIG. 16 includes the IC chip 211 and the bypass capacitor 222 which have the same characteristics as those in the circuit model of FIG. 13 and are connected with each other through a power supply path 112a and a GND path 113a. 
FIG. 17 illustrates a Z11 (impedance) characteristic in a case where the circuit model of FIG. 16 is observed from the IC chip 211. In FIG. 17, the resonance point of a low impedance in the vicinity of 100 MHz is caused by the bypass capacitor 222.
FIG. 18 illustrates enlarged portions of the graphs of FIGS. 14A and 17 in the vicinity of the resonance frequency (vicinity of 100 MHz) of the bypass capacitor 222. The resonance frequency in the graph of FIG. 14A is approximately 138 MHz, and the resonance frequency in the graph of FIG. 17 is approximately 132 MHz. That is, the resonance frequency (approximately 133 MHz) of the bypass capacitor 222 which corresponds to the characteristic thereof is shifted to approximately 138 MHz by the influence of the power supply paths 202a and 203a and the bypass capacitor 221. Therefore, when the complicated influence of another path and another electronic part are not taken into account, the resonance point of the bypass capacitor 222 cannot be accurately determined in a normal condition.
In addition, in the case of the circuit structure using the bypass capacitor as discussed in U.S. Pat. No. 6,384,476 and Japanese Patent Application Laid-Open Nos. H09-139573 and 2003-318352, when the characteristic of the bypass capacitor is changed, the characteristic of a bypass capacitor in another circuit which is electrically connected with the circuit structure is influenced by the changed characteristic. Therefore, when the characteristic of the bypass capacitor is adjusted based on a frequency at which the power ground noise is large after the completion of a printed wiring board, it is liable to vary the resonance frequency of the bypass capacitor of the electrically connected circuit, thereby increasing the noise at a frequency independent of the resonance frequency of the bypass capacitor.
FIG. 19 illustrates a circuit model obtained by omitting the bypass capacitor 222 from the circuit model of FIG. 13. FIG. 20 illustrates an S21 characteristic from the IC chip 211 to the power supply 201 in the circuit model of FIG. 19. The S21 characteristic of the circuit model of FIG. 13 is superimposed for comparison. As is apparent from FIG. 20, when the bypass capacitor 222 is attached to the circuit model of FIG. 13, the resonance frequency close to 1 GHz changes.
FIG. 21 is an enlarged portion of the graph of FIG. 20 in a range of 700 MHz to 1 GHz. As is apparent from FIG. 21, the resonance frequency in the circuit model of FIG. 13 is approximately 910 MHz. In contrast, the resonance frequency in the circuit model of FIG. 19 from which the bypass capacitor 222 is removed is approximately 870 MHz. That is, when the bypass capacitor 222 is attached, the resonance frequency close to 900 MHz changes.